In the Parallel Group, we perform research on a wide variety of areas. Some of our previous projects are listed below.

Piton Processor
Princeton Piton Processor, is a many-core designed by Prof. Wentzlaff's research group in March, 2015. It was taped-out in IBM's 32nm SOI process.

               

OpenPiton
OpenPiton is the world's first open source, general-purpose, multithreaded, manycore processor and framework. It is based on the Princeton Piton processor which was designed and taped-out in March 2015 by the Princeton Parallel Group.

               

Incentivizing Self-Capping to Increase Cloud Utilization
In this project, which was a collaboration between three research groups, we have proposed increasing the utilization of IaaS clouds by motivating tenants to fluctuate less.

               

Biodegradable Processors
In this project, we analyze the architectural tradeoffs for building biodegradable processor cores.

       

Availability Knob for IaaS Clouds
Availability Knob introduces a setting where clients can ask their desired availability and get charged correspondingly. Game theory is used to build an incentive compatible system where everyone wins. A prototype of this system was implemented in OpenStack.

               

MORC
MORC utilizes a novel log-based cache organization to compress a log composed of multiple cache lines together, gzip-style.

           

Coherence Domain Restriction
Coherence Domain Restriction (CDR) is a novel coherence framework capable of enabling systems to scale to thousands or millions of cores, while keeping constant storage overhead and high performance.

   

Execution Drafting
Execution Drafting exploits identical or similar applications that are run in data centers. The overall goal is to improve energy efficiency by trading a small performance hit due to temporally aligning threads for larger energy savings.

   

PriME: Princeton Manycore Executor
PriME is an execution-driven x86 simulator for manycore architectures. It is capable of simulating 1000+ cores with detailed cache hierarchies, coherence protocols, and network-on-chips.