The RISC-V Hardware Research Platform


Sunday afternoon, 06/23/2019, Phoenix, Arizona, USA

The Princeton Parallel Group led by David Wentzlaff and the Digital Circuits and Systems Group of ETH Zürich led by Luca Benini have joined forces to bring you the OpenPiton open-source research processor platform with first-class support for 64-bit Ariane RISC-V cores. OpenPiton is now the go-to multicore environment for Ariane. Likewise, Ariane has first-class upstream support in OpenPiton.

The combined platform, OpenPiton+Ariane, is a permissively-licensed open-source framework designed to enable scalable architecture research prototypes. With the recent addition of SMP Linux running on FPGA, OpenPiton+Ariane is the first Linux-booting, open-source, RISC-V system that scales from single-core to manycore. This makes OpenPiton+Ariane the ideal RISC-V hardware research platform.

OpenPiton began as the world’s first open source, general-purpose, multithreaded manycore processor and framework. It leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design. OpenPiton provides a complete verification infrastructure of over 8000 tests, is supported by mature software tools, runs full-stack multiuser Debian Linux, and is written in industry standard Verilog. In addition, OpenPiton provides synthesis and backend scripts for ASIC and FPGA to enable other researchers to bring their designs to implementation. Multiple implementations of OpenPiton have been created including a taped-out 25-core implementation in IBM’s 32nm process and multiple Xilinx FPGA prototypes.

It is on this mature foundation that we built OpenPiton+Ariane. Ariane is a 64-bit RISC-V application processor, which implements the RV64GC instruction set. Ariane has been taped-out in multiple foundry processes and is capable of booting Linux single-core. By modifying the L1 cache interface for Ariane to support the P-Mesh cache-coherence protocol, we built OpenPiton+Ariane into a Linux-booting, RISC-V manycore. OpenPiton+Ariane inherits all of the capabilities of OpenPiton and of Ariane, bringing them together in a single scalable, configurable, and easy-to-use platform ideal for rapid prototyping of ideas.

This tutorial will introduce the user to OpenPiton+Ariane including how to use the framework to build different designs. The tutorial will introduce the verification framework (Verilog simulation), how to synthesize a multicore OpenPiton+Ariane processor for a Xilinx FPGA board, it will demonstrate booting RISC-V Linux on an FPGA version of OpenPiton+Ariane, it will familiarize users with how to use the OpenPiton framework to target an ASIC tapeout, and it will show users how to configure and extend the OpenPiton architecture to enable architecture research.

Researchers and practitioners in academia or industry looking for a free, (permissively-licensed) open-source, RISC-V hardware platform. Common research uses include computer architecture research, EDA-tool exploration on a complex design, operating system research, and compiler research.

  1. Introduction
  2.      File Layout
  3.      Familiarization with OpenPiton+Ariane's capabilities
  4.      Familiarization with documentation
  5. Simulation
  6.      How to simulate OpenPiton+Ariane RTL
  7.      Introduction to RISC-V C/Assembly test cases
  8.      How to add C/Assembly test cases
  9.      Familiarization with test benches and monitors
  10.      Hands-on running a test case
  11. Configuration and Extension
  12.      Overview of configuration options
  13.      Hands-on configuring number of cores
  14.      Hands-on cache configuration
  15.      Discussion of different extensions
  16.           Interfacing to the NoC
  17.           Interfacing to the P-Mesh coherence protocol
  18. ASIC Synthesis and Backend
  19.      Familiarization with the OpenPiton ASIC synthesis and backend flow
  20.      Open-source Piton Characterization Data
  21. FPGA
  22.      Overview of supported boards
  23.      Overview of system-level organization (I/O and memory interfaces)
  24.      Hands-on FPGA synthesis
  25.      Hands-on Booting RISC-V Linux on OpenPiton+Ariane on FPGA
  26. Operating System and System Software
  27.      Overview of Linux boot
  28.      How to build Linux
  29. Q&A Session
  30. Closing Remarks

Attendees that wish to try out the hand-on tutorial should have a some experience with using Linux and a Linux-based text editor. Attendees should bring a laptop and charger for the tutorial. Each attendee will receive a USB flash drive containing: VirtualBox installers for Windows, Mac OS X, Linux; and a Linux virtual machine containing all of the code and tools for the tutorial, along with PDFs of the slides and handouts. Attendees will need approximately 10GB of free disk space to install and use the virtual machine.

  • Jonathan Balkind
  • Michael Schaffner
  • David Wentzlaff
  • Princeton Parallel Group Members

Linux booting on FPGA playing Tetris on OpenPiton
OpenPiton Paper
Princeton Parallel Group

            


This work was partially supported by the NSF under Grants No. CCF-1217553, CCF-1453112, and CCF-1438980, AFOSR under Grant No. FA9550-14-1-0148, and DARPA under Grants No. N66001-14-1-4040 and HR0011-13-2-0005. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of our sponsors.