| Category |
Environment/Tool |
Tested Version |
| Environment |
Operating Systems |
Springdale Linux (Custom Red Hat dist) 6.6 |
| Ubuntu 12.10 |
| Ubuntu 14.04 LTS and 16.04 LTS (Since 16-10-26-r4) |
| Unix Shells |
Bash Unix shell |
| Script Interpreters |
Python |
v2.6.6 |
| Perl |
v5.10.1 |
| Job Queue Managers |
SLURM |
v15.08.8 |
| EDA Tools |
PyHP Verilog pre-processor |
v1.12 |
| VCS Verilog simulator |
vcs_mx_I-2014.03 |
| vcs_mx_L-2016.06 (Since 16-10-26-r4) |
| Cadence Incisive Unified Simulator (NCSim) |
15.20-s037 |
| Mentor Graphics ModelSim/QuestaSim |
10.6a |
| Verilator |
4.008 |
| Icarus Verilog |
10.1.1 |
| Synopsys Design Compiler |
syn_I-2013.12-SP4 |
| Synopsys Primetime |
pt_J-2014.06 |
| Synopsys Formality |
fm_J-2014.09-SP3 |
| Synopsys IC Compiler |
icc_I-2013.12-SP4 |
| Synopsys IC Workbench Edit/View Plus |
icwbev_plus_J-2014.06 |
| Mentor Graphics Calibre |
ixl_cal_2013.2_35.25 |
| Xilinx Vivado |
2016.4 (2018.2 for Ariane) |
| Reference Methodologies(*) |
Synthesis |
DC-RM_I-2013.12-SP2 |
| Static Timing Analysis |
PT-RM_I-2013.12 |
| Place and Route |
ICC-RM_I-2013.12-SP4 |
